As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances of process parameters become more significant. Thus, for circuit designers, it is essential to estimate the influence of such variations on circuit performances and to optimise the circuit so that the maximum yield is obtained. This paper presents an approach for parametric yield optimisation of MOS VLSI circuits, in which both the simulated annealing and gradient algorithms are combined to improve the computational efficiency. With respect to other methods the proposed approach can be considered more general and robust. In addition, it is able to take deterministic parameters into account and to solve multiobjective problems. To improve the computational efficiency, the method has been implemented in a parallel computing machine based on an array of 16 transputers. Several examples of digital-and analog circuit design optimisation are reported to demonstrate the validity of the approach.

Parametric yield optimization of MOS VLSI circuits board on simulating annealing and its parallel implementation / Conti, Massimo; Orcioni, Simone; Turchetti, Claudio. - In: IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS. - ISSN 1350-2409. - STAMPA. - 141:5(1994), pp. 387-398. [10.1049/ip-cds:19941202]

Parametric yield optimization of MOS VLSI circuits board on simulating annealing and its parallel implementation

CONTI, MASSIMO;ORCIONI, Simone;TURCHETTI, Claudio
1994-01-01

Abstract

As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances of process parameters become more significant. Thus, for circuit designers, it is essential to estimate the influence of such variations on circuit performances and to optimise the circuit so that the maximum yield is obtained. This paper presents an approach for parametric yield optimisation of MOS VLSI circuits, in which both the simulated annealing and gradient algorithms are combined to improve the computational efficiency. With respect to other methods the proposed approach can be considered more general and robust. In addition, it is able to take deterministic parameters into account and to solve multiobjective problems. To improve the computational efficiency, the method has been implemented in a parallel computing machine based on an array of 16 transputers. Several examples of digital-and analog circuit design optimisation are reported to demonstrate the validity of the approach.
1994
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11566/34946
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 13
  • ???jsp.display-item.citation.isi??? 9
social impact