A new test structure for the characterization of statistical variations of the parameters of submicron MOS devices is presented in this work. The structure has been designed for the estimation of mismatch parameters as a function of the device dimensions and positions in the die. Low area consumption and a reduced measurement time required for the complete mismatch characterization are the main objective of the design. The test structure consisting of about 6000 MOSFETs has been used for mismatch characterization of a 0.18 μm CMOS technology.
A new test structure for short and long distance mismatch characterization of submicron MOS transistors / Conti, Massimo; Crippa, Paolo; Orcioni, Simone; Turchetti, Claudio; Ricciardi, F; Vece, G. B.. - 2:(2001), pp. 656-660. (Intervento presentato al convegno 44th IEEE 2001 Midwest Symposium on Circuits and Systems (MWSCAS 2001) tenutosi a Dayton, OH, U.S.A. nel 14 - 17 Agosto 2001) [10.1109/MWSCAS.2001.986274].
A new test structure for short and long distance mismatch characterization of submicron MOS transistors
CONTI, MASSIMO;CRIPPA, Paolo;ORCIONI, Simone;TURCHETTI, Claudio;
2001-01-01
Abstract
A new test structure for the characterization of statistical variations of the parameters of submicron MOS devices is presented in this work. The structure has been designed for the estimation of mismatch parameters as a function of the device dimensions and positions in the die. Low area consumption and a reduced measurement time required for the complete mismatch characterization are the main objective of the design. The test structure consisting of about 6000 MOSFETs has been used for mismatch characterization of a 0.18 μm CMOS technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
