A novel approach to statistical simulation of ICs affected by non-linear variabilities

This paper presents a methodology for statistical simulation of non-linear integrated circuits affected by device mismatch. This simulation technique is aimed at helping designers maximize yield, since it can be orders of magnitude faster than other readily available methods, e.g. Monte Carlo. DC, AC, and transient analyses are performed by means of the stochastic modified nodal analysis, using a piecewise linearization technique with respect to the stochastic sources, around a few automatically selected points.