In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the space between the dies (scribe lines) on the wafers. The test structure has been implemented in a standard 0.18-μm digital CMOS technology.
A modular test structure for CMOS mismatch characterization / Conti, Massimo; Crippa, Paolo; Fedecostante, F; Orcioni, Simone; Ricciardi, F; Turchetti, Claudio; Vendrame, L.. - 5:(2003), pp. 569-572. (Intervento presentato al convegno 2003 International Symposium on Circuits and Systems (ISCAS '03) tenutosi a Bangkok, Tailandia nel 25 - 28 Maggio 2003) [10.1109/ISCAS.2003.1206376].
A modular test structure for CMOS mismatch characterization
CONTI, MASSIMO;CRIPPA, Paolo;ORCIONI, Simone;TURCHETTI, Claudio;
2003-01-01
Abstract
In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the space between the dies (scribe lines) on the wafers. The test structure has been implemented in a standard 0.18-μm digital CMOS technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
