In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.

Parametric yield optimization of MOS ICs affected by device mismatch / Conti, Massimo; Crippa, Paolo; Orcioni, Simone; Turchetti, Claudio. - In: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. - ISSN 0925-1030. - 29:3(2001), pp. 181-199. [10.1023/A:1011213414261]

Parametric yield optimization of MOS ICs affected by device mismatch

CONTI, MASSIMO;CRIPPA, Paolo;ORCIONI, Simone;TURCHETTI, Claudio
2001-01-01

Abstract

In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11566/52693
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