An analog CMOS approximate identity neural network with stochastic learning and multilevel weight storage

In this paper CMOS VLSI circuit solutions are suggested for on-chip learning and weight storage, which are simple and silicon area efficient. In particular a stochastic learning scheme, named Random Weight Change, and a multistable weight storage approach have been implemented. Additionally, the problems of the influence of technological variations on learning accuracy is discussed. Even though both the learning scheme and the weight storage are quite general, in the paper we will refer to a class of networks, named Approximate Identity Neural Networks, which are particularly suitable to be implemented with analog CMOS circuits. As a test vehicle a small network with four neurons, 16 weights, on chip learning and weight storage has been fabricated in a 1.2um double-metal CMOS process.